Transistor size is an important part of improving computer technology. The smaller your transistors, the more you can fit on a chip, and the faster and more efficient your processor can be.
That's why it's such big news that a team at Lawrence Berkeley National Laboratory has successfully built a functional 1 nanometer long transistor gate, which the lab claims is smallest working transistor ever made.
For years, the computing industry has been governed by Moore’s Law, which states that the the number of transistors in a semiconductor circuit doubles every two years.
Current generation technology uses 14nm scale technology, with 10nm semiconductors anticipated for release in 2017 or 2018 with products like Intel’s Cannonlake line.
What is a (field effect) transistor and how does it work? A transistor is an electronic switch, the essential building block of modern digital electronics. A field-effect transistor (FET) has three terminals - a "source" (an input), a "drain" (an output) on either side of a semiconductor "channel", and a "gate" (a control knob).
If you think of electrical current like fluid flow, this is like a pipe with an inlet, and outlet, and a valve in the middle, and the gate controls the valve. In a "depletion mode" FET, the gate electrode repels away charges in the channel to turn off current between the source and drain.
In an "accumulation mode" FET, the gate attracts mobile charges into the channel to turn on current between the source and drain. Bottom line: the gate uses the electrostatic interaction with charges to control current in the channel. There has to be a thin insulating layer between the gate and the channel to keep current from "leaking" from the gate.
What's the big deal about making smaller transistors? We've gotten where we are by cramming more devices on a chip at an absurdly increasing rate, by making transistors smaller and smaller.
One key length scale is the separation between source and drain electrode. If that separation is too small, there are at least two issues: Current can leak from source to drain even when the device is supposed to be off because the charge can tunnel; and because of the way electric fields actually work, it is increasingly difficult to come up with a geometry where the gate electrode can efficiently (that is, with a small swing in voltage, to minimize power) turn the FET off and on.
What did the LBL team do? The investigators built a very technically impressive device, using atomically thin MoS2 as the semiconductor layer, source and drain electrodes separated by only seven nm or so, a ZrO2 dielectric layer only a couple of nm thick, and using an individual metallic carbon nanotube (about 1 nm in diameter) as the gate electrode. The resulting device functions quite well as a transistor, which is pretty damn cool, considering the constraints involved. This fabrication is a tour de force piece of work.
Does this device really defy physics in some way, as implied by the headline on that news article? No. That headline alludes to the issue of direct tunneling between source and drain, and a sense that this is expected to be a problem in silicon devices below the 5 nm node (where that number is not the actual physical length of the channel). This device acts as expected by physics - indeed, the authors simulate the performance and the results agree very nicely with experiment.
If you read the actual LBL press release, you'll see that the authors are very careful to point out that this is a proof-of-concept device.
That said, the research here is still in very early stages. At 14nm, a single die has over a billion transistors on it, and the Berkley Lab team has yet to develop a viable method to mass produce the new 1nm transistors or even developed a chip using them. But as a proof of concept alone, the results here are still important – that new materials can continue to allow smaller transistor sizes, and with it increased power and efficiency for the computers of the future.
